1. Field of the Invention
This invention relates to a method of analyzing and optimizing design of integrated circuit (IC) designs. In particular, the present invention relates to a method of detecting equivalent and anti-equivalent pins.
2. Description of the Related Art
An integrated circuit chip (hereafter referred to as an xe2x80x9cICxe2x80x9d or a xe2x80x9cchipxe2x80x9d) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected, thus connecting the logic circuits having the pins. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins, that must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins.
The present invention comprises a method for determining equivalent and anti-equivalent pins in a combinational circuit. A portion of a combinational circuit that includes an input of the combinational circuit, and cells that are descendants of the input, is determined. The circuit portion, including the input, and the edges of cells of the portion are duplicated. The original input is set to 1 or 0 and the duplicate input is set to the opposite. A binary decision diagram based on the portion and its duplicate is built, and then reduced.
An inverted reduced binary diagram is then formed by inverting the reduced binary decision diagram and a combined binary decision diagram is constructed by pasting the inverted reduced binary decision diagram to the original reduced binary decision diagram. This combined binary decision diagram is then reduced and equality components are located therein.